1. Field of the Invention
This invention relates to semiconductor memories and more particularly to flash EEPROM cells and the method of manufacture thereof.
2. Description of Related Art
FIGS. 1A and 1B show a prior art device as described in Samachisa et al "A 128K Flash EEPROM Using Double-Poly-silicon Technology", IEEE Solid State Circuit Vol SC-22, No. 5, pp 676-683 (Oct. 1987). FIG. 1A shows a cross section of a flash EEPROM cell 9 and FIG. 1B shows a plan view of the flash EEPROM cell 9 of FIG. 1A. Referring to FIG. 1A, EEPROM cell 9 includes two spaced apart n+ regions in the upper surface of substrate 10. Above the substrate 10 and those two n+ regions is a floating gate FG near the right hand one of the two n+ regions and above floating gate FG is the control gate CG which traverses the floating gate FG and bridges between the ends of the two n+ regions.
The drawback of the device of FIGS. 1A and 1B is that the channel length L1 of the floating gate FG and isolation transistor length L2 depend on the photolithography alignment between polysilicon 1 layer (FG) and polysilicon 2 layer (CG), even though the total channel length L=L1+L2 is fixed. In summary, the channel length is not easily controlled, because it depends upon alignment.
FIG. 2 shows a split gate prior art memory device (see U.S. Pat. No. 4,868,629) with a substrate 50 with n++ regions 54a and 54b in the surface of the substrate 50. Between the n++ regions are floating gate 52 and photoresist 53-1. The split-gate device uses photoresist 53 to form an offset channel for an isolation transistor. Therefore alignment of photoresist 53-1 with floating gate 52 determines the channel length of the isolation transistor and the total channel length of the split-gate device. The problem is the use of photoresist (53-1) to define the offset for a split-gate structure, which depends upon the alignment of the photolithography process.
Several prior art patents describing split-gate, flash EEPROM processes and structures are as follows:
U.S. Pat. No. 5,280,446 of Ma et al for "Flash EPROM Memory Circuit Having Source Side Programming;"
U.S. Pat. No. 5,274,588 of Manzur et al for "Split-Gate for an EEPROM"; and
U.S. Pat. No. 5,194,925 of Ajika et al for "Electrically Programmable Non-Volatile Semiconductor Memory Device."